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this is information on a product in full production. july 2013 docid024138 rev 5 1/21 21 STGIPS20C60 sllimm? small low-loss intelligent molded module ipm, 3-phase inverter - 20 a, 600 v short-circuit rugged igbt datasheet - production data features ? ipm 20 a, 600 v 3-phase igbt inverter bridge including control ics for gate driving and free- wheeling diodes ? short-circuit rugged igbts ? 3.3 v, 5 v, 15 v cmos/ttl inputs comparators with hysteresis and pull down / pull up resistors ? undervoltage lockout ? internal bootstrap diode ? interlocking function ? smart shutdown function ? comparator for fault protection against over temperature and overcurrent ? dbc leading to low thermal resistance ? isolation rating of 2500 v rms /min ? ul recognized: ul1557 file e81734 applications ? 3-phase inverters for motor drives ? air conditioners description this intelligent power module provides a compact, high performance ac motor drive in a simple, rugged design. combining st proprietary control ics with the most advanced short-circuit- rugged igbt system technology, this device is ideal for 3-phase inverters in applications such as motor drives and air conditioners. sllimm? is a trademark of stmicroelectronics. sdip-25l table 1. device summary order code marking package packaging STGIPS20C60 gips20c60 sdip-25l tube www.st.com
contents STGIPS20C60 2/21 docid024138 rev 5 contents 1 internal block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . 3 2 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 waveforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4 smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
docid024138 rev 5 3/21 STGIPS20C60 internal block diagram and pin configuration 1 internal block diagram and pin configuration figure 1. internal block diagram am05002v1 w nw p vboot u vboot w out v vboot v out u out w lin sd/od vcc gnd dt out hvg vboot hin lvg cp+ lin sd/od vcc gnd dt out hvg vboot hin lvg cp+ pin 16 pin 1 p p pin 17 pin 25 gnd lin-u hin-v lin-v hin-w hin-u lin-w cin vcc nu nv u v lin sd/od vcc gnd dt out hvg vboot hin lvg cp+ sd/od
internal block diagram and pin configuration STGIPS20C60 4/21 docid024138 rev 5 figure 2. pin layout (bottom view) table 2. pin description pin n symbol description 1out u high-side reference output for u phase 2v bootu bootstrap voltage for u phase 3lin u low-side logic input for u phase 4hin u high-side logic input for u phase 5v cc low voltage power supply 6out v high-side reference output for v phase 7v boot v bootstrap voltage for v phase 8 gnd ground 9lin v low-side logic input for v phase 10 hin v high-side logic input for v phase 11 out w high-side reference output for w phase 12 v boot w bootstrap voltage for w phase 13 lin w low-side logic input for w phase 14 hin w high-side logic input for w phase 15 sd / od shutdown logic input (active low) / open-drain (comparator output) 16 cin comparator input 17 n w negative dc input for w phase 18 w w phase output 19 p positive dc input 20 n v negative dc input for v phase 21 v v phase output 22 p positive dc input 23 n u negative dc input for u phase 24 u u phase output 25 p positive dc input
docid024138 rev 5 5/21 STGIPS20C60 electrical ratings 2 electrical ratings 2.1 absolute maximum ratings table 3. inverter part symbol parameter value unit v pn supply voltage applied between p - n u , n v , n w 450 v v pn(surge) supply voltage (surge) applied between p - n u , n v , n w 500 v v ces each igbt collector emitter voltage (v in (1) = 0) 1. applied between hin i , lin i and g nd for i = u, v, w 600 v i c each igbt continuous collector current at t c = 25c 20 a i cp (2) 2. pulse width limited by max junction temperature each igbt pulsed collector current 40 a p tot each igbt total dissipation at t c = 25c 46 w t scw short circuit withstand time, v ce = 0.5 v (br)ces t j = 125 c, v cc = v boot = 15 v, v in (1) = 0 - 5 v 5 s table 4. control part symbol parameter value unit v out output voltage applied between out u, out v, out w - gnd v boot - 21 to v boot + 0.3 v v cc low voltage power supply - 0.3 to +21 v v cin comparator input voltage - 0.3 to v cc +0.3 v v boot bootstrap voltage applied between v boot i - out i for i = u, v, w - 0.3 to 620 v v in logic input voltage applied between hin, lin and gnd - 0.3 to 15 v v sd /od open drain voltage - 0.3 to 15 v dv out /dt allowed output slew rate 50 v/ns table 5. total system symbol parameter value unit v iso isolation withstand voltage applied between each pin and heatsink plate (ac voltage, t = 60 sec.) 2500 v t j power chips operating junction temperature - 40 to 150 c t c module case operation temperature - 40 to 125 c
electrical ratings STGIPS20C60 6/21 docid024138 rev 5 2.2 thermal data table 6. thermal data symbol parameter value unit r thjc thermal resistance junction-case single igbt 2.7 c/w thermal resistance junction-case single diode 5 c/w figure 3. maximum i c(rms) current vs. switching frequency (1) figure 4. maximum i c(rms) current vs. f sine (1) 1. simulated curves refer to typical igbt parameters and maximum r thj-c. am17108v1 12 14 16 18 20 22 24 26 28 i c(rms) (a) 4 8 12 16 f sw (khz) 3 -phase sinusoidal pwm v pn = 300 v, modulaon index = 0.8, pf = 0.6, t j = 150 c, f sine = 60 hz tc = 80 c tc = 100 c am17109v1 8 9 10 11 12 13 14 15 16 17 i c(rms) (a) 1 10 100 f sine (hz) 3 - phase sinusoidal pwm v pn = 300 v, modulation index = 0.8, pf = 0.6, t j = 150 c, t c = 100 c fsw = 12 khz fsw = 16 khz fsw = 20 khz
docid024138 rev 5 7/21 STGIPS20C60 electrical characteristics 3 electrical characteristics t j = 25 c unless otherwise specified. note: t on and t off include the propagation delay time of the internal drive. t c(on) and t c(off) are the switching time of igbt itself under the internally given gate driving condition. table 7. inverter part symbol parameter test conditions value unit min. typ. max. v ce(sat) collector-emitter saturation voltage v cc = v boot = 15 v, v in (1) = 0 5 v, i c = 20 a -1.6 v v cc = v boot = 15 v, v in (1) = 0 5 v, i c = 20 a, t j = 125 c -1.7 i ces collector-cut off current (v in (1) = 0 ?logic state?) v ce = 550 v, v cc = v boot = 15 v - 100 a v f diode forward voltage v in (1) = 0 ?logic state?, i c = 20 a - 1.9 2.2 v inductive load switching time and energy t on turn-on time v pn = 300 v, v cc = v boot = 15 v, v in (1) = 0 5 v, i c = 20 a (see figure 5 ) -390 - ns t c(on) crossover time (on) - 170 - t off turn-off time - 970 - t c(off) crossover time (off) - 150 - t rr reverse recovery time - 284 - e on turn-on switching losses - 520 - j e off turn-off switching losses - 460 - 1. applied between hin i , lin i and g nd for i = u, v, w. (lin inputs are active-low).
electrical characteristics STGIPS20C60 8/21 docid024138 rev 5 figure 5. switching time test circuit figure 4 "switching time definition" refers to hin inputs (active high). for lin inputs (active low), v in polarity must be inverted for turn-on and turn-off. figure 6. switching time definition vboot>vcc rsd l ic vce +5v vcc input 0 1 bus /lin /sd hin vcc dt lvg hvg out boot cp+ gnd am17099v1 v ce i c i c v in t on t c(on) v in(on) 10% i c 90% i c 10% v ce (a) turn-on (b) turn-off t rr 100% i c 100% i c v in v ce t off t c(off) v in(off) 10% v ce 10% i c am09223v1
docid024138 rev 5 9/21 STGIPS20C60 electrical characteristics 3.1 control part table 8. low voltage power supply (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v cc_hys v cc uv hysteresis 1.2 1.5 1.8 v v cc_thon v cc uv turn on threshold 11.5 12 12.5 v v cc_thoff v cc uv turn off threshold 10 10.5 11 v i qccu undervoltage quiescent supply current v cc = 10 v sd /od = 5 v; lin = 5 v; h in = 0, c in = 0 450 a i qcc quiescent current v cc = 15 v sd /od= 5 v; lin = 5 v h in = 0, c in = 0 3.5 ma v ref internal comparator (cin) reference voltage 0.5 0.54 0.58 v table 9. bootstrapped voltage (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v bs_hys v bs uv hysteresis 1.2 1.5 1.8 v v bs_thon v bs uv turn on threshold 11.1 11.5 12.1 v v bs_thoff v bs uv turn off threshold 9.8 10 10.6 v i qbsu undervoltage v bs quiescent current v bs < 9 v sd /od = 5 v; lin and hin = 5 v; c in = 0 70 110 a i qbs v bs quiescent current v bs = 15 v sd /od = 5 v; lin and hin = 5 v; c in = 0 200 300 a r ds(on) bootstrap driver on resistance lvg on 120 w table 10. logic inputs (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v il low level logic threshold voltage 0.8 1.1 v v ih high level logic threshold voltage 1.9 2.25 v i hinh hin logic ?1? input bias current hin = 15 v 110 175 260 a i hinl hin logic ?0? input bias current hin = 0 v 1 a i linl lin logic ?1? input bias current lin = 0 v 3 6 20 a i linh lin logic ?0? input bias current lin = 15 v 1 a i sdh sd logic ?0? input bias current sd = 15 v 30 120 300 a i sdl sd logic ?1? input bias current sd = 0 v 3 a dt dead time see figure 7 1.2 s
electrical characteristics STGIPS20C60 10/21 docid024138 rev 5 note: x: don?t care table 11. sense comparator characteristics (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit i ib(i) input bias current v cin(i) = 1 v, i = u, v o w - 3 a v ol open-drain low-level output voltage i od = 3 ma - 0.5 v t d_comp comparator delay sd /od pulled to 5 v through 100 k resistor - 90 130 ns sr slew rate c l = 180 pf; r pu = 5 k -60 v/ sec t sd shut down to high / low side driver propagation delay v out = 0, v boot = v cc , v in = 0 to 3.3 v 50 125 200 ns t isd comparator triggering to high / low side driver turn-off propagation delay measured applying a voltage step from 0 v to 3.3 v to pin cin i 50 200 250 table 12. truth table condition logic input (v i ) output sd /od lin hin lvg hvg shutdown enable half-bridge tri-state lxxll interlocking half-bridge tri-state hlhll 0 ??logic state? half-bridge tri-state hhl l l 1 ?logic state? low side direct driving hllhl 1 ?logic state? high side direct driving hhhlh
docid024138 rev 5 11/21 STGIPS20C60 electrical characteristics 3.2 waveforms definition figure 7. dead time and interlocking waveforms definition lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg dt lh dt hl dt lh dt hl dt lh dt hl dt lh dt hl gate driver outputs off (half-bridge tri-state) interlocking interlocking control signal edges overlapped: interlocking + dead time control signals edges synchronous (*): dead time control signals edges not overlapped, but inside the dead time: dead time control signals edges not overlapped, outside the dead time: direct driving interlocking interlocking g gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state)
smart shutdown function STGIPS20C60 12/21 docid024138 rev 5 4 smart shutdown function the STGIPS20C60 integrates a comparator for fault sensing purposes. the comparator has an internal voltage reference v ref connected to the inverting input, while the non-inverting input, available on pin (c in ), can be connected to an external shunt resistor in order to implement a simple over-current protection function. when the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the halfbridge in tri-state. in the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a rc network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. the time delay between the fault and the outputs turn-off is no more dependent on the rc values of the external network connected to the shutdown pin. at the same time the dmos connected to the open-drain output (pin sd/od) is turned on by the internal logic which holds it on until the shutdown voltage is lower than the logic input lower threshold (v il ). finally the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external rc network.
docid024138 rev 5 13/21 STGIPS20C60 smart shutdown function figure 8. smart shutdown timing waveforms please refer to table 11 for internal propagation delay time details. sd/od from/to controller v bias c sd r sd smart sd logic r on_od shut down circuit r pd_sd an approximation of the disable time is given by: where: hin/lin hvg/lvg open drain gate (internal) comp vref cp+ protection fast shut down : the driver outputs are set in sd state immediately after the comparator triggering even if the sd signal has not yet reach the lower input threshold disable time sd/od am12947v1
application information STGIPS20C60 14/21 docid024138 rev 5 5 application information figure 9. typical application circuit am05001v2 cvcc w nw lin sd/od vcc gnd dt out hvg vboot hin lvg cp+ vboot v p out u vboot u out v vboot w out w rg lin sd/od vcc gnd dt out hvg vboot hin lvg cp+ lin sd/od vcc gnd dt out hvg vboot hin lvg cp+ rg rdt rg cdt rg rg rg controller cvcc rdt cdt cvcc r c rsd vdc m csd + 3.3v/5v line cbu cbv cbw vcc rshunt gnd hin-u lin-u sd/od hin-w lin-v hin-v lin-w cin vcc nu nv t1 t2 t3 t4 t5 rdt t6 v u cdt d1 d2 d3 d4 d5 d6
docid024138 rev 5 15/21 STGIPS20C60 application information 5.1 recommendations ? input signal hin is active high logic. a 85 k (typ.) pull down resistor is built-in for each high side input. if an external rc filter is used, for noise immunity, pay attention to the variation of the input signal level. ? input signal lin is active low logic. a 720 k (typ.) pull-up resistor, connected to an internal 5 v regulator through a diode, is built-in for each low side input. ? to prevent the input signals oscillation, the wiring of each input should be as short as possible. ? by integrating an application specific type hvic inside the module, direct coupling to mcu terminals without any opto-coupler is possible. ? each capacitor should be located as nearby the pins of ipm as possible. ? low inductance shunt resistors should be used for phase leg current sensing. ? electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. ? the sd /od signal should be pulled up to 5 v / 3.3 v with an external resistor (see section 4: smart shutdown function for detailed info). note: for further details refer to an3338. table 13. recommended operating conditions symbol parameter conditions value unit min. typ. max. v pn supply voltage applied between p-nu,nv,nw 300 400 v v cc control supply voltage applied between v cc -gnd 13.5 15 18 v v bs high side bias voltage applied between v booti -out i for i=u,v,w 13 18 v t dead blanking time to prevent arm-short for each input signal 1.5 s f pwm pwm input signal -40c < t c < 100c -40c < t j < 125c 20 khz t c case operation temperature 100 c
package mechanical data STGIPS20C60 16/21 docid024138 rev 5 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. please refer to dedicated technical note tn0107 for mounting instructions. table 14. sdip-25l package mechanical data dim. (mm.) min. typ. max. a 43.90 44.40 44.90 a1 1.15 1.35 1.55 a2 1.40 1.60 1.80 a3 38.90 39.40 39.90 b 21.50 22.00 22.50 b1 11.25 11.85 12.45 b2 24.83 25.23 25.63 c 5.00 5.40 6.00 c1 6.50 7.00 7.50 c2 11.20 11.70 12.20 e 2.15 2.35 2.55 e1 3.40 3.60 3.80 e2 4.50 4.70 4.90 e3 6.30 6.50 6.70 d 33.30 d1 5.55 e11.20 e1 1.40 f 0.85 1.00 1.15 f1 0.35 0.50 0.65 r 1.55 1.75 1.95 t 0.45 0.55 0.65 v0 6
docid024138 rev 5 17/21 STGIPS20C60 package mechanical data figure 10. sdip-25l package dimensions 8154676_h
package mechanical data STGIPS20C60 18/21 docid024138 rev 5 figure 11. packaging specifications of sdip-25l package am10488v1 base quantity: 11 pcs bulk quantity: 132 pcs 8123127_e
docid024138 rev 5 19/21 STGIPS20C60 package mechanical data figure 12. sdip-25l shipping tube type b (dimensions are in mm.) antis tatic s 03 pvc am10487v1 8123127_e base quantity: 11 pcs bulk quantity: 132 pcs
revision history STGIPS20C60 20/21 docid024138 rev 5 7 revision history table 15. document revision history date revision changes 08-mar-2013 1 initial release 20-mar-2013 2 added figure 3 and figure 4 on page 6 . 17-jun-2013 3 updated dt value in table 10: logic inputs (vcc = 15 v unless otherwise specified) , figure 7: dead time and interlocking waveforms definition and t dead in table 13: recommended operating conditions . 09-jul-2013 4 updated dt value in table 10: logic inputs (vcc = 15 v unless otherwise specified) . 16-jul-2013 5 updated table 2: pin description , table 8: low voltage power supply (vcc = 15 v unless otherwise specified) and table 9: bootstrapped voltage (vcc = 15 v unless otherwise specified)
docid024138 rev 5 21/21 STGIPS20C60 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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